PSA: Seeed XIAO HaLow (FGH100M-H): enumerates fine, RX fine, TX dead? Wire the 5V pad (VDD_FEM)

If you’re wiring a Seeed XIAO Wi-Fi HaLow board (Wi-Fi_Halow_FGH100M_EXT01, FGH100M-H / MM6108) to a Raspberry Pi over SPI, every tutorial and forum thread I could find shows only 3V3 + GND for power. After many sessions debugging asymmetrically weak TX, the actual answer was in the Seeed schematic: this board has two separate power rails, and you need both.

Per the Quectel FGH100M-H spec:

  • VBAT (digital baseband): typ. 3.3 V
  • VDD_IO (digital I/O): typ. 3.3 V
  • VDD_FEM (front-end module — the TX power amplifier): typ. 5 V, range 3.0–5.25 V

On the XIAO HaLow board (schematic WI-FI_HALOW_FGH100M_EXT01_V30_SCH_20241107.pdf):

  • VBAT and VDD_IO come off MOD_3V3 via ferrite bead FB1 (decoupled by C8/C9) — the 3V3 pad.
  • VDD_FEM comes off MOD_5V via ferrite bead FB2 (C3/C5/C6) — the 5V pad, which the tutorials don’t mention.

Wire only 3V3 + GND and you get a chip that enumerates cleanly, loads firmware, brings up a full S1G phy, and receives great — but the PA is starved, so TX is ~40 dB weaker than the driver thinks it’s commanding. Peers can’t see the node in batctl o / iw station dump even at 1-inch antenna spacing.

The fix is one wire: Pi pin 2 (or 4) 5V → the XIAO HaLow’s 5V pad. TX came up instantly — strong signal both directions, clean bidirectional traffic at 30+ Mbps link estimates.

Diagnostic signature (distinguishes this from everything it imitates):

  • Chip enumerates, phy shows full S1G capabilities ✓
  • RX works — peers visible at strong signal up close ✓
  • TX dead at any range — peers never see you ✗
  • Total system current barely rises during ping -f (the PA can’t draw)
  • vs. brown-out: varies with power supply; this is constant across PSUs
  • vs. bad antenna: attenuates RX equally; this is RX-fine / TX-dead

Bonus: the board-side pad map, since forum recipes for the WM1302/WM6108 mPCIe carrier don’t apply to this board, and multimeter probing misleads (RESET has ESD diodes too — it reads like the INT pad). From the schematic, the only authority:

XIAO pad FGH100M signal note
D0 RESET_N via R13 0Ω; R15 = 10K pulldown → chip held in reset by default
D1 WAKEUP_IN R10 DNP — not connected
D2 SPI_INT R11 0Ω
D3 SPI_CS R21 0Ω
D4 BUSY R17 DNP — not connected
D8 SPI_CLK R14 22Ω
D9 SPI_MISO R12 22Ω
D10 SPI_MOSI R16 22Ω

Because of R15, the driver must actively drive RESET high — a reset released to input floats low and the chip never wakes. And since WAKE/BUSY aren’t connected (DNP), run the driver with enable_ps=0.

Two practical extras for hand-wired setups:

  • Start at spi_clock_speed=4000000. After soldering (not flying leads) we ramped empirically: clean scaling to 40 MHz (~6× throughput); 50 MHz fails to init on point-to-point wiring even though it’s the driver default on PCB-traced carriers.
  • If your mesh peers share a frequency but can’t see each other, check morse_cli -i wlanN channel — the Primary Channel Index must match on every node.

No existing thread or wiki page documents the 5V requirement for this board — hope this saves the next person the weeks it cost me.

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