I was looking at the PCB layout of a project in the MMECH17 Design Package (based on MM8108), when I noticed that the SDIO net doesn’t have Controlled Impedance Routing enabled, and it uses the default track width and clearances.
When I tried to calculate the impedance (Single Coplanar, Clearance = 0.152mm, Width = 0.254mm, with solder mask 0.02mm), it seemed to be outside the 50 Ohm (±10%) target. Maybe I missed something?
If it actually is outside the expected range, did you check how it affects performance/signal quality? Also, would you recommend adding impedance control for SDIO in derived projects?
SDIO is an interesting case. It is not designed around impedance controlled traces in the same way that RF signals or protocols such as USB are. However, it is not immune to the laws of physics and signal integrity issues from impedance mismatch will still affect it. The source will typically be driven by a low impedance (in the order of ohms) and terminated by a high impedance (hundreds of kilo-ohms or higher). So there is no single matching that will minimize reflections in the same way that a RF trace is always impedance matched.
For best performance we recommend that you design your traces to be designed around something and that this impedance is consistent along the trace and between traces in the SDIO, This will minimize timing mismatches and that you will have consistent behavior. We often recommend 50R out of convenience - your EDA will already have rules for 50R that are being used for HaLow, so you can use the same rules on SDIO.
The requirements for this impedance control is less important for SDIO than it is for HaLow. You don’t need to get the PCB house to guaranteed the 50R spec, just make sure that at design time you have given the impedance control your best effort, and this will often get you a lot of signal integrity gains at little effort.